CBGA Packaging Analysis

This is a model of part of a 4S7P 13 layer ceramic ball grid array (CBGA) integrated circuit package mounted on a printed circuit board. The IC die and low inductance cell array (LICA) capacitor are simply modeled as homogeneous blocks. The model was gridded with 25 micron cells, resulting in a grid of size 316 X 329 X 112, and a simulation size of 730 megabytes. The simulation was run for 80 nanoseconds, requiring 30 minutes of computation on a CRAY J90. Thanks to Roger Gravrok of Sequent Computer Systems for providing this example.

Top part of the model, isolated The large gray box on the top left is a portion of the integrated circuit die, connected to the package with C4 balls in "flip-chip" fashion. The smaller gray box on the right is the capacitor. The green cross-hatch is the meshed package ground plane. A similar layer for the power plane is not shown.	Package layer 3, isolated The blue traces shown here are in package layer 3. The interconnects highlighted in white form a differential signal pair that are routed up from the PCB, through this layer, and into the IC. The rose and lime vertical interconnects are power and ground vias. The signal vias are shown in yellow.
BSM layer, isolated This is the bottom surface metal pad layer of the circuit board. The large rings are the pads, placed with a 50-mil pitch.	Complete model On top are the die and capacitor, mounted on the four-layer package interconnect, all within the CBGA. The CBGA itself is mounted on the printed circuit board, which is shown at the bottom.

Upper ground plane current density at t=38ps Blue=0 A/M2, Red=10e6 A/M2	Lower ground plane current density at t=54ps Blue=0 A/M2, Red=10e6 A/M2
BSM current density at t=56ps	R3 current density at t=73ps.

Quicktime Movies

• CBGA upper ground layer currents (3.4mb)
• CBGA lower ground layer currents (4.5mb)
• Routing layer 3 currents (0.7mb)
• BSM layer currents (1.6mb)

Models

• CBGA Java wireframe model
• CBGA 3-D VRML model