Table of Contents
·Hardware Description Language Comparison ·Not Gate ·Xor Gate ·Concatenation ·Bit Selection ·Repetition ·2-Input Mux ·4-Input Mux ·Adder ·Unsigned Multiplier ·Signed Multiplier ·Equal Comparison ·Unsigned Less-Than Comparison ·Signed Less-Than Comparison ·Assertion ·4-Bit Register ·Truth Table ·State Machine ·Component Definition ·Component Instantiation

Hardware Description Language Comparison

This is a list of common hardware constructs.

Not Gate

HDCaml	let x = ~: a
Confluence	x = '~' a
Verilog	assign x = ~a;
VHDL	x <= not a;

Xor Gate

HDCaml	let x = a ^: b
Confluence	x = a '^' b
Verilog	assign x = a ^ b;
VHDL	x <= a xor b;

Concatenation

HDCaml	let x = a ++ b
Confluence	x = a '++' b
Verilog	assign x = {a, b};
VHDL	x <= a & b;

Bit Selection

HDCaml	let sel0 = bit sig_in 0 let sel1 = select sig_in 7 4
Confluence	sel0 = sig_in'[0] sel1 = sig_in'[7:4]
Verilog	assign sel0 = sig_in[0]; assign sel1 = sig_in[7:4];
VHDL	sel0 <= sig_in(0); sel1 <= sig_in(7 downto 4);

Repetition

HDCaml	let x = repeat a 4
Confluence	x = a '#' 4
Verilog	assign x = {4{a}};
VHDL	x <= (others => 'a');

2-Input Mux

HDCaml	let x = mux2 switch on_high on_low
Confluence	x = switch 'then' on_high 'else' on_low
Verilog	assign x = switch ? on_high : on_low
VHDL	x <= on_high when switch = '1' else on_low;

4-Input Mux

HDCaml	let x = mux select [sig0 sig1 sig2 sig3]
Confluence	x = {mux select [sig0 sig1 sig2 sig3] $}
Verilog	always @ (select or sig0 or sig1 or sig2 or sig3) case (select) 2'b00: x = sig0; 2'b01: x = sig1; 2'b10: x = sig2; default: x = sig3; endcase
VHDL	process (sel, sig0, sig1, sig2, sig3) begin case sel is when "00" => x <= sig0; when "01" => x <= sig1; when "10" => x <= sig2; others => x <= sig3; end case; end process;

Adder

HDCaml	let x = a +: b
Confluence	x = a '+' b
Verilog	assign x = a + b;
VHDL	x <= a + b;

Unsigned Multiplier

HDCaml	let x = a *: b
Confluence	x = a '*' b
Verilog	assign x = {4'b0000, a} * {4'b0000, b};
VHDL	x <= unsigned(a) * unsigned(b);

Signed Multiplier

HDCaml	let x = a *+ b
Confluence	x = a '*+' b
Verilog	assign x = {{4{a[3]}}, a} * {{4{b[3]}}, b};
VHDL	x <= signed(a) * signed(b);

Equal Comparison

HDCaml	let x = a ==: b
Confluence	x = a '==' b
Verilog	assign x = a == b;
VHDL	x <= '1' when a = b else '0';

Unsigned Less-Than Comparison

HDCaml	let x = a <: b
Confluence	x = a '<' b
Verilog	assign x = a < b;
VHDL	x <= '1' when unsigned(a) < unsigned(b) else '0';

Signed Less-Than Comparison

HDCaml	let x = a <+ b
Confluence	x = a '<+' b
Verilog	assign x = ({~a[3], a[2:0]} < {~b[3], b[2:0]}) ? 1'b1 : 1'b0;
VHDL	x <= '1' when signed(a) < signed(b) else '0';

Assertion

HDCaml	assertion "assertion_error_message" (always (prop test_signal))
Confluence	{assert "Assertion error message." test_signal}
Verilog	always @ (test_signal) if (!test_signal) $display("Assertion error message.")
VHDL	process (test_signal) begin assert test_signal = '1' report "Assertion error message." severity error; end process;

4-Bit Register

HDCaml	let sig_out = reg enable sig_in
Confluence	{reg 4 sig_in sig_out}
Verilog	reg [3:0] sig_out always @ (posedge clock) if (reset = 1) sig_out <= 0; else if (enable = 1) sig_out <= sig_in;
VHDL	process (clock) begin if clock'event and clock = '1' then if reset = '1' then sig_out <= "0000"; elsif enable = '1' then sig_out <= sig_in; end if; end if; end process;

Truth Table

Confluence

{truth_table [["0011" "00"]
              ["0100" "01"]
              ["1000" "11"]
              ["1111" "10"]] sig_in sig_out}

Verilog

always @ (sig_in)
  case sig_in
    4'b0011: sig_out = 2'b00;
    4'b0100: sig_out = 2'b01;
    4'b1000: sig_out = 2'b11;
    default: sig_out = 2'b10;
  endcase

VHDL

process (sig_in)
begin
  case sig_in is
    when "0011" => sig_out <= "00";
    when "0100" => sig_out <= "01";
    when "1000" => sig_out <= "11";
    when others => sig_out <= "10";
  end case;
end process;

State Machine

Confluence

                    
{state_machine [["00" 0 0 "0"]                      
                ["01" 0 0 "0"]                    
                ["10" 0 1 "1"]                    
                ["11" 0 0 "0"]                   
                ["00" 1 1 "1"]                  
                ["01" 1 0 "0"]                
                ["10" 1 1 "1"]               
                ["11" 1 0 "0"]] sig_in sig_out}

Verilog

always @ (sig_in or state)
  case {sig_in, state}
    3'b000: sig_out = 1'b0;
    3'b010: sig_out = 1'b0;
    3'b100: sig_out = 1'b1;
    3'b110: sig_out = 1'b0;
    3'b001: sig_out = 1'b1;
    3'b011: sig_out = 1'b0;
    3'b101: sig_out = 1'b1;
    default: sig_out = 1'b0;
  endcase

always @ (clock)
  if (reset = 1)
    state <= 1'b0;
  else if (enable = 1)
    case {sig_in, state}
      3'b000: state <= 1'b0;
      3'b010: state <= 1'b0;
      3'b100: state <= 1'b1;
      3'b110: state <= 1'b0;
      3'b001: state <= 1'b1;
      3'b011: state <= 1'b0;
      3'b101: state <= 1'b1;
      default: state <= 1'b0;
    endcase

VHDL

process (sig_in, state)
begin
  case (sig_in & state) is
    when "000" => sig_out <= '0';
    when "010" => sig_out <= '0';
    when "100" => sig_out <= '1';
    when "110" => sig_out <= '0';
    when "001" => sig_out <= '1';
    when "011" => sig_out <= '0';
    when "101" => sig_out <= '1';
    when others => sig_out <= '0';
  end case;
end process;

process (clock)
begin
  if clock'event and clock = '1' then
    if reset = '1' then
      state <= '0';
    elsif enable = '1' then
      case (sig_in & state) is
        when "000" => state <= '0';
        when "010" => state <= '0';
        when "100" => state <= '1';
        when "110" => state <= '0';
        when "001" => state <= '1';
        when "011" => state <= '0';
        when "101" => state <= '1';
        when others => state <= '0';
      end case;
    end if;
  end if;
end process;

Component Definition

HDCaml	let reg_adder a b = reg vdd (a +: b)
Confluence	component reg_adder +a +b -x is {reg 4 (a '+' b) x} end
Verilog	module reg_adder (clock, enable, reset, a, b, x); input clock; input enable; input reset; input [3:0] a; input [3:0] b; output [3:0] x; reg [3:0] x; wire [3:0] add_result; assign add_result = a + b; always @ (posedge clock) if (reset) x <= 4'b0000; else if (enable) x <= add_result; endmodule
VHDL	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity reg_adder is port( signal clock : in std_logic; signal enable : in std_logic; signal reset : in std_logic; signal a : in unsigned(3 downto 0); signal b : in unsigned(3 downto 0); signal x : out unsigned(3 downto 0) ) end entity reg_adder; architecture rtl of registered_adder is signal add_result : unsigned(3 downto 0); begin add_result <= a + b; process (clock) begin if clock'event and clock = '1' then if reset = '1' then x <= "0000"; elsif enable = '1' then x <= add_result; end if; end if; end process; end architecture rtl;

Component Instantiation

HDCaml	let reg_adder4 a b c d = reg_adder (reg_adder a b) (reg_adder c d)
Confluence	component reg_adder4 +a +b +c +d -x is {reg_adder {reg_adder a b $} {reg_adder c d $} x} end
Verilog	module reg_adder_4 (clock, enable, reset, a, b, c, d, x); input clock; input enable; input reset; input [3:0] a; input [3:0] b; input [3:0] c; input [3:0] d; output [3:0] x; wire [3:0] add_result_ab; wire [3:0] add_result_cd; reg_adder add_ab (clock, enable, reset, a, b, add_result_ab); reg_adder add_cd (clock, enable, reset, c, d, add_result_cd); reg_adder add_result (clock, enable, reset, add_result_ab, add_result_cd, x); endmodule
VHDL	add_ab : reg_adder port map (clock, enable, reset, a, b, c, d, x);